1. Field of the Invention
The present invention relates to a cascade-type variable-order delta-sigma modulator. In particular, the present invention relates to a cascade-type variable-order delta-sigma modulator having quantization loops connected in a cascade configuration and changing the number of stages of the quantization loops depending on peripheral circuitries to be connected thereto.
2. Description of the Related Art
In recent years, an analog-to-digital converter and a digital-to-analog converter for use in a digital-audio device, including a delta-sigma modulator, are widely spread. The analog-to-digital converter and the digital-to-analog converter are combined with various circuits and integrated on a single substrate such as a LSI circuit (a large-scale integrated circuit) or the like, to reduce size, weight, and cost of the entire digital-audio device. The analog-to-digital converter is combined with an analog input circuit, such as a microphone input amplifying circuit, a line input circuit or the like. The digital-to-analog converter is combined with, for example, an amplifying circuit for a loudspeaker, a line output circuit or the like.
Performance of the entire digital-audio device is decided depending on the lowest signal-to-noise ratio (hereinafter, referred to as a SNR) among those of the delta-sigma modulator and peripheral circuitries combined with the delta-sigma modulator, such as an input circuit, an output circuit. Thereby, the SNR of the delta-sigma modulator should be higher than those of the peripheral circuitries. There is a demand for raising SNR of a delta-sigma modulator to realize a digital-audio device with high-performance as performance of the peripheral circuitries increases.
Although the SNR of the delta-sigma modulator can be raised by increasing the order of integrator in quantization loop incorporated in the delta-sigma modulator, a high order integrator causes instability of the operation of the delta-sigma modulator. In addition, although the SNR of the delta-sigma modulator can be raised by increasing the oversampling ratio, a high oversampling ratio narrows the bandwidth and causes a negative effect on transmission rate. Disclosed is a cascade-type delta-sigma modulator with stability and high-performance wherein a plurality of quantization loops, each having an integrator of relatively low order (e.g. second-order or less), are connected in a cascade configuration. (See Japanese patent laid-open publication No. 2004-080152.)
FIG. 10 shows a configuration of an analog-to-digital converter including a cascade-type delta-sigma modulator of a prior art. In FIG. 10, a selector 3 selects an input signal from an input circuit 1 or an input signal from an input circuit 2 in compliance with a control signal CS from a digital signal processor (DSP) 104 and transmits the selected signal to a delta-sigma modulator 107 as an analog input signal X. The delta-sigma modulator 107 includes a first quantization loop 101 having a first-order integrator 131, a subtracter 121, a second quantization loop 102 having a second-order integrator 132, and a noise rejecting circuit 111.
The first quantization loop 101, quantizes the analog input signal X by the first-order integrator 131 and a quantizer 141, and outputs a quantization signal Y1 to the noise rejecting circuit 111. The digital-to-analog converting unit 151 converts the quantization signal Y1 to an analog signal before feeding a negative feedback to a subtracter 1311. The subtracter 121 subtracts a signal level of an output signal of the digital-to-analog converting unit 151 from a signal level of an output signal of the first-order integrator 131, and outputs the subtraction result to the second quantization loop 102 as a quantization error signal A.
The second quantization loop 102 quantizes the quantization error signal A from the subtracter 121 by the second-order integrator 132 and a quantizer 142, and outputs a quantization signal Y2. The digital-to-analog converting unit 152 converts the quantization signal Y2 to an analog signal before feeding a negative feedback to subtracters 1321 and 1323.
The noise rejecting circuit 111 differentiates the quantization signal Y2 by a differentiator 171, adds a signal level of the quantization signal Y1 to a signal level of the differentiated quantization signal Y2 by the adder 161, and outputs a quantization signal Y which is the addition result to a digital filtering circuit 5.
As described above, the cascade-type delta-sigma modulator of the prior art has such a configuration that a plurality of the quantization loops, each having an integrator of relatively low order, are connected in a cascade configuration. In the cascade-type delta-sigma modulator of the prior art, the quantization error of the first quantization loop 101 is inputted to the second quantization loop 102, and thus, a high SNR is realized keeping stability of the delta-sigma modulator even if an oversampling rate is low.